1. Field of the Invention
This invention relates to an improved image sensor array. More particularly, the invention relates to such an image sensor array where each picture element sensor circuit in the array may be tested with controllable reset voltage signals applied to the photo-sensitive element in each sensor circuit.
2. Description of Related Art
Conventional focal plane image scanner arrays are tested in the same manner as they are used in the field. An image of specific light intensity is applied to the image scanner and each row of the image scanner is read out to measure the strength of the photoelectric signal detected by each picture element (pixel) sensor circuit at each pixel position. Accordingly in a two dimensional array of sensors, to test the sensors each row of the array must be illuminated at different illumination levels as desired for the test and each pixel sensor must be read out at each illumination level. As might be appreciated, this is a time-consuming process requiring precision in illumination as well as the normal precision in reading out signals from the array.
FIG. 1 illustrates a simple design for a conventional array. The array has columns A-N, and rows 1-n. Thus each pixel sensor circuit can be denoted by the column letter and the row number. Accordingly, the pixel sensor circuit at the second column and the second row would be denoted as B2.
Each of the pixel sensor circuits is connected to a column line 10, 12 or 14 in FIG. 1. Each column line is driven by the pixel sensor circuit, e.g., A1 on column line 10 through a load field effected transistor (FET) 16. The load FET is biased by a voltage. V.sub.L to provide a given resistance to the column line. The output of the pixel sensor circuit is taken off the column line and is the voltage drop across the load FET.
To read out this type of array the road access drivelines row 1 through row n are sequentially enabled. The output voltage across the load FET for each column line is then observed to detect the illumination that is sensed at the pixel sensor in that column for the row driven by the row access line which was enabled.
A simple pixel sensor circuit is illustrated as the A1 pixel sensor in FIG. 1. This pixel sensor operates by having the reset FET 18 enabled by the reset signal to bring the voltage at node 20 to V.sub.DD less the voltage drop across FET 18. V.sub.DD is typically 3-5 volts and the voltage drop across FET 18 is about 7/10 of a volt. Photo diode 22 is thus back biased by the voltage on node 20. As light shines on the photo diode 22, charge across the junction of the photo diode 22 leaks away and the voltage at node 20 drops. The voltage at node 20 after a given time of exposure to light on photo diode 22 is a measure of the light intensity detected by the photo diode 22.
FET 24 with the load FET 16 on column line 10 acts as a source follower circuit to output a voltage proportional to the voltage at node 20 on the output line 26 at load FET 16. Pixel sensor circuit A1 is selected by the ROW 1 signal enabling FET 28. Thus FET 28 is acting simply as a switch in the source follower circuit made up of FET 24 with a load resistance provided by the load FET 16. The small-signal gain of the source follower is about 0.85.
As just described, each of the pixel sensors in FIG. 1 in the past was tested by resetting each sensor and providing a different level of illumination in successive tests at each photo diode 22 in sensor array.
While this is workable, it is tedious and requires a good bit of precision control of the illumination provided during testing.